This invention relates generally to a data output circuit of a semiconductor memory device and, more particularly to a circuit for matching an equalizing level of data lines in a pair with a logic threshold voltage of data output buffers.
Generally, data is read out and written from/into a memory cell of a semiconductor memory device by selecting a word line and a bit line, and then transferred to the exterior of a chip. The data read out is amplified by a sense amplifier and then, is output to the exterior via a data output circuit.
Referring to FIG. 1, shown is a conventional data output circuit for outputting data stored on the memory cell to the exterior of the chip. The data stored on the memory cell 1 is amplified by a sense amplifier 2. The data output from the sense amplifier 2 is input to circuits 3 and 5 each having four MOS transistors controlled by a pair of selection control signals MSi and/MSi. The circuits 3 and 5 are respectively configured to have two PMOS transistors (3a, 3b; 5a, 5b) connected in series to the power supply voltage Vcc and two NMOS transistors (3c, 3d; 5c, 5d) connected in series to the ground voltage Vss. In case of the circuit 3, if the selection control signal MSi and the data on the line 1 are at the logic "high", the PMOS transistor 3aand the NMOS transistors 3c, 3d are all turned on and the PMOS transistor 3b is turned off, so that a voltage at a first node NO1 goes to the logic "low". On the contrary, a voltage at a second node /NO1 goes to the logic "high". To increase a sensing speed of the data, the voltages at the first and second nodes NO1 and/NO1 are initially equalized by an NMOS transistor 11 upon receiving an address transition detection pulse PEQ (i.e., an equalizing signal) at a gate thereof.
If a buffer enable signal PIO of the logic "low" is applied to first and second data output buffers each comprised of NAND gates 13 and 15, the outputs of the NAND gates 13 and 15 are both at the logic "high". Thus, the voltages at third and fourth nodes NO2, /NO2 go to the logic "low" and accordingly, pull-up and pull-down NMOS transistors 17 and 19 are both turned off. However, if the buffer enable signal PIO goes to the logic "high", the outputs of the NAND gates 13 and 15 become "high" and "low" respectively and as a result, the NMOS transistors 17 and 18 are respectively turned off and turned on. Thus, the output data becomes at the logic "low".
However, when the equalizing levels of the first and second nodes NO1 and/NO1 do not match with a logic threshold voltage (or a triggering voltage) of the first and second data output buffers 13 and 15, problems are raised which will be explained hereinbelow with reference to FIGS. 2A and 2B.
Referring first to FIG. 2A, shown is a case where the equalizing level of the voltages at the first and second nodes NO1 and/NO1 is set to be higher than the logic threshold voltage of the data output buffers 13 and 15. In this case, when the potential difference between the first and second nodes NO1 and/NO1 is not developed (i.e., the voltages at NO1 and/NO1 are equalized), the input voltages of the respective nodes NO1 and/NO1 may be both misrecognized as the logic "high". At this moment, if the buffer enable signal PIO changes to the logic "high", the NMOS transistors 17 and 19 are both turned on, resulting in a realoperation of the data output circuit.
Referring to FIG. 2B, illustrated is a case where the equalizing level of the voltages at the first and second nodes NO1 and/NO1 is lower than the logic threshold voltage of the data output buffers 13 and 15. In this case, it takes longer for a potential at the first or second node NO1,/NO1 to become at the logic "high" level, upon receiving data from the sense amplifier 2. Accordingly, the operation time of the data output buffers 13 and 15 is delayed after the buffer enable signal PIO enabled to the logic "high", reducing the overall operation speed of the data output circuit. A letter "L" representing the data output time interval (time delay) of FIG. 2B is normally 2ns. Thus, it is needed to match the equalizing level of the data lines in a pair with the logic threshold voltage of the data output buffers. However, it becomes extremely difficult to match them since the equalizing level of the voltages at the data lines varies according to the various process parameters of the memory device.